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June 1999
PBL 386 50/2 Subscriber Line Interface Circuit
Description
The PBL 386 50/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated circuit for use in Central Office Metering applications and other telecommunications equipment. The PBL 386 50/2 has been optimized for low total line interface cost and a high degree of flexibility in different applications. The PBL 386 50/2 emulates resistive loop feed, programmable between 2x50 and 2x900 , with short loop current limiting adjustable to max 45 mA. In the current limited region the loop feed is nearly constant current with a slight slope corresponding to 2x30k. A second, lower battery voltage may be connected to the device to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external components or external control. The SLIC incorporates loop current, ground key and ring trip detection functions. The PBL 386 50/2 is compatible with both loop and ground start signaling. Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is accomplished by the SLIC in conjunction with either a conventional CODEC/filter or with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable two-wire impedance, complex or real, is set by a simple external network. Longitudinal voltages are suppressed by a feedback loop in the SLIC and the longitudinal balance specifications meet Bellcore TR909 requirements. The PBL 386 50/2 package options are 24-pin SSOP, 24-pin SOIC or 28-pin PLCC.
Key Features
* 24-pin SSOP package * Programmable two-wire signal headroom for 2.2 Vrms metering * High and low battery with automatic switching * Only +5 V feed in addition to battery * Selectable transmit gain (0.5x or 0.25x) * 70 mW on-hook power dissipation in active state * On-hook transmission * Long loop battery feed tracks Vbat for maximum line voltage * No power-up sequence * 43V open loop voltage @ -48V battery feed * Constant loop voltage for line leakage <5 mA (RLeak ~ >10 k @ -48V) * Full longitudinal current capability during on-hook state * Analog over temperature protection permits transmission while the protection circuit is active * Line voltage measurement
Ring Relay Driver RRLY
* Polarity reversal * Ground key detector * Tip open state with ring ground detector
DT DR TIPX RINGX HP
Ring Trip Comparator Input Decoder and Control
C1 C2 C3 DET
Ground Key Detector
VCC
P B L
LP PLD REF VTX
VBAT2 VBAT Off-hook Detector
PBL
386
50/2
AGND BGND VF Signal Transmission
RSN
PTG
24-pin SOIC, 24-pin SSOP, 28-pin PLCC
Figure 1. Block diagram.
1
38 PB 6L 50 /2
Two-wire Interface
Line Feed Controller and Longitudinal Signal Suppression
POV PSG PLC
38 6
50 /2
PBL 386 50/2
Maximum Ratings
Parameter Symbol Min Max Unit
Temperature, Humidity Storage temperature range Operating temperature range Operating junction temperature range, Note 1 Power supply, 0C TAmb -70C VCC with respect to A/BGND VBat2 with respect to A/BGND VBat with respect to A/BGND, continuous VBat with respect to A/BGND, 10 ms Power dissipation Continuous power dissipation at TAmb +70 C Ground Voltage between AGND and BGND Relay Driver Ring relay supply voltage Ring trip comparator Input voltage Input current Digital inputs, outputs (C1, C2, C3, DET) Input voltage Output voltage TIPX and RINGX terminals, 0C < TAmb < +70C, VBat = -50V Maximum supplied TIPX or RINGX current TIPX or RINGX voltage, continuous (referenced to AGND), Note 2 TIPX or RINGX, pulse < 10 ms, tRep > 10 s, Note 2 TIPX or RINGX, pulse < 1 s, tRep > 10 s, Note 2 TIPX or RINGX, pulse < 250 ns, tRep > 10 s, Notes 2 & 3
TStg TAmb TJ VCC VBat2 VBat VBat PD VG
-55 -40 -40 -0.4 VBat -75 -80
+150 +110 +140 6.5 0.4 0.4 0.4 1.5
C C C V V V V W V
-0,3
0,3
BGND+14 V VDT, VDR IDT, IDR VID VOD ITIPX, IRINGX VTA, VRA VTA, VRA VTA, VRA VTA, VRA VBat -5 -0.4 -0.4 AGND 5 VCC VCC +100 2 5 10 15 V mA V V
-100 -80 VBat -10 VBat -25 VBat -35
mA V V V V
Recommended Operating Condition
Parameter Symbol Min Max Unit
Ambient temperature VCC with respect to AGND VBat with respect to AGND AGND with respect to BGND
TAmb VCC VBat VG
0 4.75 -65 -100
+70 5.25 -8 100
C V V mV
Notes
1. 2. 3. The circuit includes thermal protection. Operation at or above 140C junction temperature may degrade device reliability. With the diodes DVB and DVB2 included, see figure 12. RF1 and RF2 20 is also required. Pulse is applied to TIP and RING outside RF1 and RF2.
2
PBL 386 50/2
Electrical Characteristics
0 C TAmb +70 C, PTG = Open (see pin description), ROV = , VCC= +5V 5 %, VBat= -58V to -40V, VBat2 = -32V, RLC=32.4 k, IL = 27 mA. RL = 600 , RF1= RF2= RP1= RP2=0, RRef = 49.9 k, CHP = 47 nF, CLP=0.15 F, RT = 60 k, RSG = 0 k, RRX = 60 k, RR = 11 k unless otherwise specified. Current definition: current is positive if flowing into a pin.
Parameter Ref fig Conditions Min Typ Max Unit
Two-wire port Overhead voltage, VTRO ,ILdc > 18mA On-Hook, ILdc < 5mA Over load level, metering Input impedance, ZTR Longitudinal impedance, ZLOT, ZLOR Longitudinal current limit, ILOT, ILOR Longitudinal to metallic balance, BLM (IEEE standard 455-1985, ZTRX=736) Longitudinal to metallic balance, BLME ELo BLME = 20 * Log VTR Longitudinal to four-wire balance, BLFE BLFE = 20 * Log ELo VTX 4 2 Active state, ROV = 0.2 kHz < f < 3.4 kHz 1% THD, Note 1 f16kHz, ZLAC =200, Adj. by ROV Note 2 0 < f < 100 Hz active state Normal polarity: 0.2 kHz < f < 1.0 kHz 1.0 kHz < f < 3.4 kHz Reverse polarity: 0.2 kHz < f < 3.4 kHz Normal polarity: 0.2 kHz < f < 1.0 kHz 1.0 kHz < f < 3.4 kHz Reverse polarity: 0.2 kHz < f < 3.4 kHz 0.2 kHz < f < 3.4 kHz 2.7 1.1 5.0 ZT/200 20 18 55 55 55 61 61 61 40 75 70 68 50 35 VPeak VPeak VPeak /wire mArms /wire dB dB dB dB dB dB dB
3
3
Metallic to longitudinal balance, BMLE VTR BMLE = 20 * Log ; ERX = 0 VLo
C
TIPX
VTX
Figure 2. Overhead voltage, VTRO, twowire port
1 << RL, RL= 600 C RT = 60 k, RRX = 60 k
RL
VTRO
ILDC
PBL 386 50/2
RINGX RSN
RT
E RX
RRX
TIPX ELo
VTX
Figure 3. Longitudinal to metallic (BLME) and Longitudinal to four-wire (BLFE) balance 1 << 150 , RLR =RLT =RL /2=300 C
RT = 60 k, RRX = 60 k
C
RLT V TR RLR RINGX RSN RRX
PBL 386 50/2
RT
V TX
3
PBL 386 50/2
Ref fig
Parameter
Conditions
Min
Typ
Max
Unit
Four-wire to longitudinal balance, BFLE
4
0.2 kHz < f < 3.4 kHz E BFLE = 20 * Log RX VLo r = 20 * Log |ZTR + ZL| |ZTR - ZL|
40
50
dB
Two-wire return loss, r
TIPX idle voltage, VTi RINGX idle voltage, VRi VTR Four-wire transmit port (VTX) Overhead voltage, VTXO, IL > 18mA On-hook, IL < 5mA Output offset voltage, VTX Output impedance, zTX Four-wire receive port (RSN) Receive summing node (RSN) DC voltage Receive summing node (RSN) impedance Receive summing node (RSN) current (IRSN) to metallic loop current (IL) gain,RSN Frequency response Two-wire to four-wire, g2-4 6 5
0.2 kHz < f < 1.0 kHz 1.0 kHz < f < 3.4 kHz, Note 3 active, IL <5 mA active, IL <5 mA tip open, IL <5 mA active, IL<5 mA Load impedance > 20 k, 1% THD, Note 4
27 20
35 22 - 1.3 VBat +3.0 VBat +3.0 VBat +4.3
dB dB V V V V VPeak VPeak mV V ratio
1.35 0.55 -100
0.2 kHz < f < 3.4 kHz IRSN = -155 A 0.2 kHz < f < 3.4 kHz 0.3 kHz < f < 3.4 kHz 1.15
0 15 1.25 8 200
100 50 1.35 20
relative to 0 dBm, 1.0 kHz. ERX = 0 V 0.3 kHz < f < 3.4 kHz f = 8.0 kHz, 12 kHz, 16 kHz
-0.20 -1.0
0.10 0.1
dB dB
TIPX C VLo RLT V TR RLR RINGX
VTX
PBL 386 50/2
RSN
RT
Figure 4. Metallic to longitudinal and fourwire to longitudinal balance
E RX
RRX
1 << 150 , RLT =RLR =RL /2 =300 C RT = 60 k, RRX = 60 k
C RL ILDC EL
TIPX
VTX
PBL 386 50/2
RINGX RSN
RT
VTXO
Figure 5. Overhead voltage, VTXO, fourwire transmit port
1 << RL, RL = 600 C RT = 60 k, RRX = 60 k
RRX
4
PBL 386 50/2
Ref fig
Parameter
Conditions
Min
Typ
Max
Unit
Four-wire to two-wire, g4-2
6
Four-wire to four-wire, g4-4 Insertion loss Two-wire to four-wire, G2-4
6
relative to 0 dBm, 1.0 kHz. EL=0 V 0.3 kHz < f < 3.4 kHz f = 8 kHz, 12 kHz, 16 kHz relative to 0 dBm, 1.0 kHz, EL=0 V 0.3 kHz < f < 3.4 kHz 0 dBm, 1.0 kHz, Note 5 V G2-4 = 20 * Log TX ; ERX = 0 VTR PTG = AGND 0 dBm, 1.0 kHz, Note 6 V G4-2 = 20 * Log TR ; EL = 0 ERX Ref. -10 dBm, 1.0 kHz, Note 7 -40 dBm to +3 dBm -55 dBm to -40 dBm Ref. -10 dBm, 1.0 kHz, -40 dBm to +3 dBm -55 dBm to -40 dBm C-message weighting, 2 wire Psophometrical weighting, 2 wire C-message weighting, 4 wire Psophometrical weighting, 4 wire Note 8
-0.2 -1.0 -2.0 -0.2
0.1 0 0 0.1
dB dB dB dB
6
-6.22 -12.24 -0.2
-6.02 -12.04
-5.82 -11.84 0.2
dB dB dB
Four-wire to two-wire, G4-2
6
Gain tracking Two-wire to four-wire
6
-0.1 -0.2 -0.1 -0.2
0.1 0.2 0.1 0.2 12 -78 6 -84
dB dB dB dB dBrnC dBmp dBrnC dBmp
Four-wire to two-wire
6
Noise Idle channel noise at two-wire (TIPX-RINGX) or four-wire (VTX) output
Harmonic distortion Two-wire to four-wire Four-wire to two-wire Battery feed characteristics Loop current, IL , in the current limited region, reference A, B & C Tip open state TIPX current, ILeak Tip open state RINGX current, ILRTo Tip open state RINGX voltage, VRTo
6
0 dBm 0.3 kHz < f < 3.4 kHz
-67 -67
-50 -50
dB dB
13 7
18mA IL 45 mA S = closed; R = 7 k, Note 10 RLRTo = 0, VBat = -48V RLRTo = 2.5 k, VBat = -48V ILRTo < 23 mA
0.92 IL
IL
1.08 IL -150
mA A mA mA V
IL 17 VBat +6
Figure 6. Frequency response, insertion loss, gain tracking.
1 << RL, RL = 600 C RT = 60 k, RRX = 60 k
C
TIPX
VTX
RL VTR EL ILDC
PBL 386 50/2
RINGX RSN
RT
E RX
VTX
RRX
5
PBL 386 50/2
Ref fig
Parameter
Conditions
Min
Typ
Max
Unit
Tip voltage (ground start) Tip voltage (ground start)
7
Open circuit state loop current, ILOC Loop current detector Programmable threshold, ILTh, active, active reverse Tip open state
Active state, Tip lead open (S open), Ring lead to ground through 150 Active state, tip lead to -48 V through 7 k (S closed), Ring lead to ground through 150 RL = 0 ILTh = 500 RLD RLD in k, ILTh 7 mA ILTh = 500 RLD
-4 -6
-2.2 -2.4
V V
-100 0.85*ILTh
0 ILTh
100 1.15*ILTh
A mA
0.85*ILTh
ILTh
1.15*ILTh
mA
Ground key detector Ground key detector threshold (ILTIPX and ILRINGX difference to trigger ground key det.) 10 Line voltage measurement Pulse width, tLVM Note 9 Ring trip comparator Offset voltage, VDTDR Source resistance, RS = 0 -20 Input bias current, IB IB = (IDT + IDR)/2 -200 Input common mode range, VDT, VDR VBat+1 Ring relay driver Saturation voltage, VOL IOL = 50 mA Off state leakage current, ILk VOH = 12 V Digital inputs (C1, C2, C3) Input low voltage, VIL 0 Input high voltage, VIH 2.5 Input low current, IIL VIL = 0.5 Input high current, IIH VIH = 2.5 V Detector output (DET) Output low voltage IOL = 0.5 mA Internal pull-up resistor Power dissipation (VBat = -48V, VBat2 = -32V) P1 Open circuit state, C1, C2, C3 = 0, 0, 0 Active state, C1, C2, C3 = 0, 1, 0 P2 Longitudinal current = 0 mA, I L=0 mA (on-hook) P3 RL = 300 (off-hook) P4 RL = 800 (off-hook) Power supply currents (VBat = -48V) VCC current, ICC Open circuit state VBat current, IBat -0.1 VCC current, ICC Active state VBat current, IBat On-hook, Long Current = 0 mA -1.5 Power supply rejection ratios VCC to 2- or 4-wire port Active State 30 VBat to 2- or 4-wire port f = 1 kHz Vn = 100mV 36 VBat2 to 2- or 4-wire port 40 Temperature guard Junction threshold temperature, TJG Thermal resistance 28-pin PLCC, JP28plcc 24-pin SOIC, JP24soic 24-pin SSOP, JP24ssop 6
16 5.5 0 -20
22
mA s/V
20 200 -1 0.5 10 0.5 VCC -50 50 0.7
mV nA V V A V V A A V k mW mW mW mW mA mA mA mA dB dB dB C C/W C/W C/W
0.2
15 10 70 730 360 1.2 -0.05 2.8 -1.1 42 45 60 145 39 43 55 15 85
2.0 4.0
PBL 386 50/2
R
VBExt
S
TIPX
PBL 386 50/2 RLRTo
RINGX
Figure 7. Tipx voltage.
Notes
1. The overhead voltage can be adjusted with the ROV resistor for higher levels e.g. min 3.1 VPeak and is specified at the two-wire port with the signal source at the four-wire receive port. The two-wire impedance is programmable by selection of external component values according to: ZTRX = ZT/|G2-4S RSN| where: ZTRX = impedance between the TIPX and RINGX terminals ZT = programming network between the VTX and RSN terminals G2-4S = transmit gain, nominally = 0.5 (or 0.25 see pin PTG) RSN = receive current gain, nominally = 200 (current defined as positive flowing into the receivesumming node, RSN, and when flowing from ring to tip). Higher return loss values can be achieved by adding a reactive component to RT, the two-wire terminating impedance programming resistance, e.g. by dividing RT into two equal halves and connecting a capacitor from the common point to ground. The overhead voltage can be adjusted with the ROV resistor for higher levels e.g. min 1.6 VPeak and is specified at the four-wire transmit port, VTX, with the signal source at the two-wire port. Note that the gain from the two-wire port to the four-wire transmit port is G2-4S = 0.5 (or 0.25 see pin PTG). The overhead voltage is dependent on G2-4S and POV setting. 5. Pin PTG = Open sets transmit gain to nom. -6.02dB Pin PTG = AGND sets transmit gain to nom. -12.04 dB Secondary protection resistors RF and resistors RP impact the insertion loss as explained in the text, section Transmission. The specified insertion loss is for RF = RP = 0. 6. The specified insertion loss tolerance does not include errors caused by external components. 7. The level is specified at the two-wire port. 8. The two-wire idle noise is specified with the port terminated in 600 (RL) and with the four-wire receive port grounded (ERX = 0; see figure 6). The four-wire idle noise at VTX is specified with the twowire port terminated in 600 (RL). The noise specification is referenced to a 600 programmed two-wire impedance level at VTX. The four-wire receive port is grounded (ERX = 0). 9. Previous state must be active - loop or ground key detector. 10. If |VBExt| |VBat + 2 V|, where VBat is the voltage at VBAT pin, the current ILeak is limited to 5mA.
2.
3.
4.
7
PBL 386 50/2
2 RRLY
RRLY 2 HP 3 RINGX 4 BGND 5 TIPX 6 VBAT 7 VBAT2 8 PSG 9 LP 10 DT 11 DR
12
23 AGND 22 RSN 21 REF
RINGX BGND TIPX VBAT VBAT2 PSG NC
5 6 7 8 9 10 11
26 RSN
PTG
28 VTX
NC
4
3
HP
PTG 1
24 VTX
27 AGND
1
25 24
NC REF PLC POV PLD VCC NC
24-pin SOIC 20 PLC and 19 POV 24-pin SSOP
18 PLD 17 VCC 16 DET 15 C1
28-pin PLCC
23 22 21 20 19
12
DT 13
DR 14
C3 15
C2 16
C1 17
14 C2
13
C3
Figure 8. Pin configuration, 24-pin SSOP, 24-pin SOIC and 28 pin PLCC package, top view.
Pin Description
Refer to figure 8.
PLCC Symbol Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14
PTG RRLY HP NC RINGX BGND TIPX VBAT VBAT2 PSG NC LP DT DR
Progr.Transmit Gain. Left open transmit gain = -6.02 dB, connected to AGND transmit gain = -12.04 dB. Ring Relay driver output. The relay coil may be connected to maximum +14V. Connection for High Pass filter capacitor, CHP. Other end of CHP connects to TIPX. No internal Connection The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components and ring relay (and optional test relay). Battery Ground, should be tied together with AGND. The TIPX and RINGX pins connect to the tip and ring leads of the two-wire interface via overvoltage protection components and ring relay (and optional test relay). Battery supply Voltage. Negative with respect to AGND. An optional second (2) Battery Voltage connects to this pin. Programmable Saturation Guard. The resistive part of the DC feed characteristic is programmed by a resistor connected from this pin to VBAT. No internal Connection Connection for Low Pass filter capacitor, CLP. Other end of CLP connects to VBAT. Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level low, indicating off-hook condition. The external ring trip network connects to this input. Input to the ring trip comparator. With DR more positive than DT the detector output, DET, is at logic level low, indicating off-hook condition. The external ring trip network connects to this input.
8
DET 18
LP
PBL 386 50/2
15 16 17 18 19 20 21 22 C3 C2 C1 DET
}
C1, C2 and C3 are digital inputs (internal pull-up) controlling the SLIC operating states. Refer to section "Operating states" for details. Detector output. Active low when indicating loop detection and ring trip, active high when indicating ground key detection. No internal Connection +5 V power supply. Programmable Loop Detector threshold. The loop detection threshold is programmed by a resistor connected from this pin to AGND. Programmable Overhead Voltage. If pin is left open: The overhead voltage is internally set to min 2.7 V in off-hook and min 1.1 V in On-hook. If a resistor is connected between this pin and AGND: the overhead voltage can be set to higher values. Prog. Line Current, the current limit,reference C in figure 13, is programmed by a resistor connected from this pin to AGND. A Reference, 49.9 k, resistor should be connected from this pin to AGND. No internal Connection Receive Summing Node. 200 times the AC-current flowing into this pin equals the metallic (transversal) AC-current flowing from RINGX to TIPX. Programming networks for two-wire impedance and receive gain connect to the receive summing node. A resistor should be connected from this pin to AGND. Analog Ground, should be tied together with BGND. Transmit vf output. The AC voltage difference between TIPX and RINGX, the AC metallic voltage, is reproduced as an unbalanced GND referenced signal at VTX with a gain of 0.5 (or 0.25, see pin PTG). The two-wire impedance programming network connects between VTX and RSN.
NC VCC PLD POV
23 24 25 26
PLC REF NC RSN
27 28
AGND VTX
SLIC Operating States
State 0 1 2 3 4 5 6 7 C3 0 0 0 0 1 1 1 1 C2 0 0 1 1 0 0 1 1 C1 0 1 0 1 0 1 0 1 SLIC operating state Open circuit Ringing state Active state Active state Tip open state Active state Active reverse Active reverse Active detector Ring trip detector (active low) Loop detector (active low) Line voltage measurement (note 9) Loop detector (active low) Ground key detector (active high) Loop detector (active low) Ground key detector (active high)
Table 1. SLIC operating states.
9
PBL 386 50/2
Four-Wire to Two-Wire Gain
TIPX RF ZL VTR ZTR RHP RP
+
TIP
IL
+
RF RP IL RINGX G 2-4S
VTX
+
VTX ZT
+
RING EL
From (1), (2) and (3) with EL = 0: VTR = VRX Z ZL - T ZT ZRX + G2 - 4S ( ZL + 2RF + 2R P ) RSN
G4 -2 =
-
Z RX RSN I L /RSN
+
VRX
PBL 386 50/2
Figure 9. Simplified ac transmission circuit.
-
For applications where ZT/(RSN*G2-4S) + 2RF + 2RP is chosen to be equal to ZL the expression for G4-2 simplifies to: Z 1 G4 -2 = - T Z RX 2G2 - 4S Four-Wire to Four-Wire Gain From (1), (2) and (3) with EL = 0: V G4 -4 = TX = VRX
-
Functional Description and Applications Information
Transmission
General A simplified ac model of the transmission circuits is shown in figure 9. Circuit analysis yields:
VTR = VTX + IL (2R F + 2RP ) G2 - 4S
determines the SLIC TIPX to RINGX impedance at voice frequencies. ZRX controls four- to two-wire gain. VRX is the analog ground referenced receive signal. RSN is the receive summing node current to metallic loop current gain = 200. Note that the SLICs two-wire to fourwire gain, G2-4S, is user programmable between two fix values. Refer to the datasheets for values on G2-4S. Two-Wire Impedance To calculate ZTR, the impedance presented to the two-wire line by the SLIC including the fuse and protection resistors RF and RP, let VRX = 0. From (1) and (2): ZT Z TR = + 2RF + 2RP RSN G 2- 4S Thus with ZTR, RSN, G2-4S, RP and RF known: Z T = RSN G2- 4S (Z TR - 2RF - 2R P ) Two-Wire to Four-Wire Gain From (1) and (2) with VRX = 0:
G2- 4 = VTX = VTR Z T / RSN ZT + 2RF + 2RP RSN G2 - 4S
ZT
ZT ZRX
G 2- 4S ( Z L + 2RF + 2R P ) ZT + G2 -4 S ( ZL + 2RF + 2RP ) RSN
Hybrid Function The hybrid function can easily be implemented utilizing the uncommitted amplifier in conventional CODEC/filter combinations. Please, refer to figure 10. Via impedance ZB a current proportional to VRX is injected into the summing node of the combination CODEC/filter amplifier. As can be seen from the expression for the four-wire to four-wire gain a voltage proportional to VRX is returned to VTX. This voltage is converted by RTX to a current flowing into the same summing node. These currents can be made to cancel by letting: VTX VRX + = 0(EL = 0 ) R TX ZB The four-wire to four-wire gain, G4-4, includes the required phase shift and thus the balance network ZB can be calculated from:
V ZB = -RTX RX = VTX ZT + G2 -4 S ( ZL + 2RF + 2RP ) ZRX RSN R TX ZT G2 -4 S ( ZL + 2RF + 2RP )
(1) (2) (3)
VTX VRX I + =L ZT Z RX RSN
VTR = EL - IL * ZL
where: VTX is a ground referenced version of the ac metallic voltage between the TIPX and RINGX terminals. G2-4S is the programmable SLIC two-wire to four-wire gain (transmit direction). See note below. VTR is the ac metallic voltage between tip and ring. EL is the line open circuit ac metallic voltage. is the ac metallic current. IL RF is a fuse resistor. RP is part of the SLIC protection ZL is the line impedance.
When choosing RTX, make sure the output load of the VTX terminal is >20k.
10
PBL 386 50/2
If calculation of the ZB formula above yields a balance network containing an inductor, an alternate method is recommended. Contact Ericsson Microelectronics for assistance. The PBL 386 50/2 SLIC may also be used together with programmable CODEC/filters. The programmable CODEC/filter allows for system controller adjustment of hybrid balance to accommodate different line impedances without change of hardware. In addition, the transmit and receive gain may be adjusted. Please, refer to the programmable CODEC/filter data sheets for design information. Longitudinal Impedance A feed back loop counteracts longitudinal voltages at the two-wire port by injecting longitudinal currents in opposing phase. Thus longitudinal disturbances will appear as longitudinal currents and the TIPX and RINGX terminals will experience very small longitudinal voltage excursions, leaving metallic voltages well within the SLIC common mode range. The SLIC longitudinal impedance per wire, ZLoT and ZLoR, appears as typically 20 to longitudinal disturbances. It should be noted that longitudinal currents may exceed the dc loop current without disturbing the vf transmission. Capacitors CTC and CRC The capacitors designated CTC and CRC in figure 12, connected between TIPX and ground as well as between RINGX and ground, can be used for RFI filtering. The recommended value for CTC and CRC is 2200 pF. Higher capacitance values may be used, but care must be taken to prevent degradation of either longitudinal balance or return loss. CTC and CRC contribute to a metallic impedance of 1/(*f*CTC) = 1/(*f*CRC), a TIPX to ground impedance of 1/(2**f*CTC) and a RINGX to ground impedance of 1/(2**f*CRC).
RFB
VTX
RTX VT ZT Z RX ZB
PBL 386 50/2
Combination CODEC/Filter
V RX
RSN
Figure 10. Hybrid function.
AC - DC Separation Capacitor, CHP The high pass filter capacitor connected between terminals HP and TIPX provides the separation of the ac signal from the dc part. CHP positions the low end frequency response break point of the ac loop in the SLIC. Refer to table 1 for recommended values of CHP. Example: A CHP value of 150 nF will position the low end frequency response 3dB break point of the ac loop at 1.8 Hz (f3dB) according to f3dB = 1/(2**RHP*CHP) where RHP = 600 k. High-Pass Transmit Filter The capacitor CTX in figure 12 connected between the VTX output and the CODEC/filter forms, together with RTX and/or the input impedance of a programmable CODEC/filter, a high-pass RC filter. It is recommended to position the 3 dB break point of this filter between 30 and 80 Hz to get a faster response for the dc steps that may occur at DTMF signalling. Capacitor CLP The capacitor CLP, which connects between the terminals CLP and VBAT, positions together with the resistive loop feed resistor RSG (see section Battery Feed), the high end frequency break point of the low pass filter in the dc loop in the SLIC. CLP together with RSG, CHP and ZT (see section Two-Wire Impedance) forms the total two wire output impedance of the SLIC. The choise of these programmable components have an influence on the power supply rejection ratio (PSRR) from VBAT to the two wire side at sub-audio frequencies. At these frequencies capacitor CLP also influences the transversal to longitudinal balance in the SLIC. Table 1 suggests suitable values on CLP for different feeding characteristics. Typical values of the transversal to longitudinal balance (T-L bal.) at 200Hz is given in table 1 for the chosen values on CLP.
RFeed [] 2*50 2*200 2*400 2*800
RSG [k] 0 60.4 147 301
CLP [nF] 150 100 47 22
T-L bal. @200Hz [dB] -46 -46 -43 -36
CHP [nF] 47 150 150 150
Table 1. RSG , CLP and CHP values for different feeding characteristics.
11
PBL 386 50/2
Battery Feed
The PBL 386 50/2 SLIC emulate resistive loop feed, programmable between 2*50 and 2*900 , with adjustable current limitation. In the current limited region the loop current has a slight slope corresponding to 2*30 k, see figure 13 reference B. The open loop voltage measured between the TIPX and RINGX terminals is tracking the battery voltage VBat. The signalling headroom, or overhead voltage VTRO, is programmable with a resistor ROV connected between terminal POV on the SLIC and ground. Please refer to section "Programmable overhead voltage(POV)". The battery voltage overhead, VOH, depends on the programmed signal overhead voltage VTRO. VOH defines the TIP to RING voltage at open loop conditions according to VTR(at IL = 0 mA) = |VBat| - VOH. Refer to table 2 for typical values on VOH and VOHVirt. The overhead voltage is changed when the line current is approaching open loop conditions. To ensure maximum open loop voltage, even with a leaking telephone line, this occurs at a line current of approximately 6 mA. When the overhead voltage has changed, the line voltage is kept nearly constant with a steep slope corresponding to 2*25 (reference G in figure 13). The virtual battery overhead, VOHVirt, is defined as the difference between the battery voltage and the crossing point of all possible resistive feeding slopes, see figure 13 reference J. The virtual battery overhead is a theoretical constant needed to be able to calculate the feeding characteristics. SLIC VOH(typ) [V] VOHVirt(typ) [V] 4.9 +VTRO The current limit (reference C in figure 13) is adjusted by connecting a resistor, RLC, between terminal PLC and ground according to the equation: RLC = 1000 ILProg + 4 receive output via the resistor RRX, is dc biased with +1.25V. This makes it possible to compensate for currents floating due to dc voltage differences between RSN and the CODEC output without using any capacitors. This is done by connecting a resistor RR between the RSN terminal and ground. With current directions defined as in figure 14, current summation gives:
-IRSN = IRT + IRRX + IRR = 1 25 125 - VCODEC , , 125 , + + RT RRX RR
where RLC is in k for ILProg in mA. A second, lower battery voltage may be connected to the device at terminal VBAT2 to reduce short loop power dissipation. The SLIC automatically switches between the two battery supply voltages without need for external control. The silent battery switching occurs when the line voltage passes the value |VB2| - 40*IL - (VOHVirt -1.3), if IL > 6 mA. For correct functionality it is important to connect the terminal VBAT2 to the second power supply via the diode DVB2 in figure 12. An optional diode DBB connected between terminal VB and the VB2 power supply, see figure 12, will make sure that the SLIC continues to work on the second battery even if the first battery voltage disappears. If a second battery voltage is not used, VBAT2 is connected to VBAT on the SLIC and CVB2, DBB and DVB2 are removed.
where VCODEC is the reference voltage of the CODEC at the receive output. From this equation the resistor RR can be calculated as
RR = 125 , , 1 25 125 - VCODEC , - - RT RRX
-IRSN
For values on IRSN, see table 3. The resistor RR has no influence on the ac transmission. SLIC PBL 386 50/2 IRSN [A] -155
Metering applications
For designs with metering applications please contact Ericsson Microelectronics for assistance. CODEC Receive Interface The PBL 386 50/2 SLIC have got a completely new receive interface at the four wire side which makes it possible to reduce the number of capacitors in the applications and to fit both single and dual battery feed CODECs. The RSN terminal, connecting to the CODEC
12 11 10 9 8 7 6 5 4 3 2 1 0
Table 3. The SLIC internal bias current with the direction of the current defined as positive when floating into the terminal RSN.
Programmable overhead voltage(POV) With the POV function the overhead voltage can be increased. If the POV pin is left open the overhead voltage is internally set to 3.2 VPeak in off-
PBL 386 50/2 3.0 +VTRO
VTRO (VPeak)
Table 2. Battery overhead.
The resistive loop feed (reference D in figure 13) is programmed by connecting a resistor, RSG, between terminals PSG and VBAT according to the equation: RFeed = RSG + 2*104 + 2RF 200
off-hook on-hook
0
10
20
where RFeed is in for RSG and RF in .
30 Rov (K)
40
50
60
Figure 11. Programmable overhead voltage (POV). RL = 600 or .
12
PBL 386 50/2
hook and 1.3 VPeak on-hook. If a resistor ROV is connected between the POV pin and AGND, the overhead voltage can be set to higher values, typical values can be seen in figure 11. The ROV and corresponding VTRO (signal headroom) are typical values for THD <1% and the signal frequency 1000Hz. Observe that the 4-wire output terminal VTX can not handle more than 3.2 VPeak. So if the gain 2-wire to 4-wire is -6.02dB, 6.4 VPeak is maximum also for the 2-wire side. Signal levels between 6.4 and 12.8 VPeak on the 2-wire side can be handled with the PTG shorted so that the gain G2-4S become -12.04dB. Please note that the 2-wire impedance, RR and the 4-wire to 4-wire gain has to be recalculated if the PTG is shorted. Please note that the maximum signal current at the 2-wire side can not be greater than 29 mA. How to use POV: 1. Decide what overhead voltage(VTRO) is needed. The POV function is only needed if the overhead voltage exceeds 3.2 VPeak 2. In figure 11 the corresponding ROV for the decided VTRO can be found. 3. If the overhead voltage exceeds 6.4 VPeak , the G2-4S gain has to be changed to -12.04dB by connecting the PTG pin to AGND. Please note that the two-wire impedance, RR and the 4-wire to 4-wire gain has to be recalculated. Analog Temperature Guard The widely varying environmental conditions in which SLICs operate may lead to the chip temperature limitations being exceeded. The PBL 386 50/2 SLIC reduce the dc line current when the chip temperature reaches approximately 145C and increases it again automatically when the temperature drops. Accordingly transmission is not lost under high ambient temperature conditions. The detector output, DET, is forced to a logic low level when the temperature guard is active.
R FB
PBL 386 50/2
C TX KR +12 V /+5V C GG RING R F2 R P2
RINGX REF PTG VTX
R TX 0
RRLY
AGND
RT R RX
RB
+
+
HP
RSN
0
D HP
C HP
NC NC
RR R REF R LC R OV R LD VCC C VCC PBL 386 50/2 C RC
CODEC/ Filter
TIP
R F1
OVP
VB C TC
BGND
PLC
TIPX
POV
R P1
VBAT PLD
D VB2 VB2 D BB D VB VB C VB E RG R1 R RT
DT C2 VBAT2 VCC
R SG C VB2 C LP
LP C1 PSG NC
VCC
NC
DET
R2 C1 C2
DR
C3
R3
R4 SLIC No. 2 etc.
SYSTEM CONTROL INTERFACE
RESISTORS: (Values according to IEC E96 series) =0 1% 1/10 W RSG = 49.9 k 1% 1/10 W RLD ROV = User programmable = 32.4 k 1% 1/10 W RLC = 49.9 k 1% 1/10 W RREF RR = 11.5 k 1% 1/10 W = 52.3 k 1% 1/10 W RT = 32.4 k 1% 1/10 W RTX RB = 57.6 k 1% 1/10 W = 52.3 k 1% 1/10 W RRX Depending on CODEC / filter RFB R1 = 604 k 1% 1/10 W = 604 k 1% 1/10 W R2 = 249 k 1% 1/10 W R3 R4 = 280 k 1% 1/10 W = 330 5% 2 W RRT 10 1% 1/10 W (Note 1) RP1, RP2 RF1, RF2 = Line resistor, 40 1% match
CAPACITORS: (Values according to IEC E96 series) = 100 nF 100 V 10% CVB = 150 nF 100 V 10% CVB2 CVCC = 100 nF 10 V 10% = 2.2 nF 100 V 10% CTC = 2.2 nF 100 V 10% CRC CHP = 47 nF 100 V 10% = 150 nF 100 V 10% CLP = 68 nF 10 V 10% CTX CGG = 220 nF 100 V 10% = 330 nF 63 V 10% C1 = 330 nF 63 V 10% C2 DIODES: DVB DVB2 DBB DHP = 1N4448 = 1N4448 = 1N4448 = 1N4448 (Note 2)
OVP: Secondary protection ( e.g. Power Innovations TISPPBL2). The ground terminals of the secondary protection should be connected to the common ground on the Printed Board Assembly with a track as short and wide as possible, preferable a groundplane. NOTES: 1. RP1 and RP2 may be omitted if DVB is in place. 2. It is required to connect DHP between terminal HP and ground if CHP >47nF.
Figure 12. Single-channel subscriber line interface with PBL 386 50/2 and combination CODEC/filter.
13
PBL 386 50/2
DC characteristics
A
A
B
C
B
C
I L [mA]
D
D
E G F F H
J
V TR [V]
A: IL (@ VTR = 0V) = ILProg + |VBat| - VOHVirt - RFeed * (ILProg + 4*10-3) 60 * 103 E: F: B: C: RfeedB = 2 * 30 k ILConst(typ) = ILProg = 103 RLC G: - 4*10-3 H: J: VTROpen = |VBat| - VOH Virtual battery VBatVirt (@ IL = 4 mA) = |VBat| - VOHVirt IL 6 mA Apparent battery VBat(@ IL = 0) =|VBat| - VOHVirt - (RFeed * 4*10-3) RfeedG = 2 * 25
VTR = |VBat| - VOHVirt - RFeed * (ILProg + 4*10-3) RSG + 2 * 104 200
D:
RFeed =
Figure 13. Battery feed characteristics (without the protection resistors on the line).
Loop Monitoring Functions
The loop current, ground key and ring trip detectors report their status through a common output, DET. The detector to be connected to DET is selected via the three bit wide control interface C1, C2 and C3. Please refer to section Control Inputs for a description of the control interface. Loop Current Detector The loop current detector is indicating that the telephone is off hook and that current is flowing in the loop by putting the output DET to a logical low level when selected. The loop current threshold value, ILTh, at which the loop current detector changes state is programmable by selecting the value of resistor RLD. RLD connects between pin PLD and ground
and is calculated according to 500 RLD = ILTh The current detector is internally filtered and is not influenced by the ac signal at the two wire side. Ground Key Detector The ground key detector is indicating when the ground key is pressed (active) by putting the output pin DET to a logical high level when selected. The ground key detector circuit senses the difference in TIPX and RINGX currents. When the current at the RINGX side exceeds the current at the TIPX side with the threshold value the detector is triggered. For threshold current values, please refer to the datasheet.
Ring Trip Detector Ring trip detection is accomplished by connecting an external network to a comparator in the SLIC with inputs DT and DR. The ringing source can be balanced or unbalanced superimposed on VB or GND. The unbalanced ringing source may be applied to either the ring lead or the tip lead with return via the other wire. A ring relay driven by the SLIC ring relay driver connects the ringing source to tip and ring. The ring trip function is based on a polarity change at the comparator input when the line goes off-hook. In the onhook state no dc current flows through the loop and the voltage at comparator input DT is more positive than the voltage at input DR. When the line goes off-hook, while the ring relay is ener-
14
PBL 386 50/2
gized, dc current flows and the comparator input voltage reverses polarity. Figure 12 gives an example of a ring trip detection network. This network is applicable, when the ring voltage is superimposed on VB and is injected on the ring lead of the two-wire port. The dc voltage across sense resistor RRT is monitored by the ring trip comparator input DT and DR via the network R1, R2, R3, R4, C1 and C2. With the line on-hook (no dc current) DT is more positive than DR and the DET output will report logic level high, i.e. the detector is not tripped. When the line goes off-hook, while ringing, a dc current will flow through the loop including sense resistor RRT and will cause input DT to become more negative than input DR. This changes output DET to logic level low, i.e. tripped detector condition. The system controller (or line card processor) responds by de-energizing the ring relay, i.e. ring trip. Complete filtering of the 20 Hz ac component at terminal DT and DR is not necessary. A toggling DET output can be examined by a software routine to determine the duty cycle. When the DET output is at logic level low for more than half the time, off-hook condition is indicated.
PBL386 50/2
I
VTX DC-GND RT CODEC
IRT RSN +1.25 V IRSN IRRX R RX _ + IRR UREFcodec
RR
Figure 14. CODEC receive interface.
Ringing State The ring relay driver and the ring trip detector are activated and the ring trip detector is indicating off hook with a logic low level at the detector output. The SLIC is in the active normal state. Active States TIPX is the terminal closest to ground and sources loop current while RINGX is the more negative terminal and sinks loop current. Vf signal transmission is normal. The loop current or the ground key detector is activated. The loop current detector is indicating off hook with a logic low level and the ground key detector is indicating active ground key with a logic high level present at the detector output. In PBL 386 50/2 a line voltage measurement feature is available in the active state, which may be used for line length estimations or for line test purposes. The line voltage is presented on the detector output as a pulse at logic high level with a pulsewidth of 5.5 s/V. To start the line voltage measurement this mode has to be entered from the Active State with the loop or ground key detector active. The pulse presented at the DET output proportional to the line voltage starts when entering the line voltage measuring mode. Tip Open State Tip Open State is used for ground start signalling. In this state the SLICs present a high impedance to the line on the TIPX pin and the programmed dc characteristic, with the longitudinal current compensation (see section Longitudinal Impedance) not active, to the line on the RINGX pin. The loop current detector is active. Active Polarity Reversal State TIPX and RINGX polarity is reversed from the Active State: RINGX is the terminal closest to ground and sources loop current while TIPX is the more negative terminal and sinks current. Vf signal transmission is normal. The loop current or the ground key detector is activated. The loop current detector is indicating off hook with a logic low level and the ground key detector is indicating active ground key with a logic high level present at the detector output.
Relay driver
The PBL 386 50/2 SLIC incorporates a ring relay driver designed as open collector (npn) with a current sinking capability of 50mA. The drive transistor emitter is connected to BGND. The relay driver has an internal zener diode clamp for inductive kickback voltages. Care must be taken when using the relay driver together with relays that have high impedance.
Overvoltage Protection
The PBL 386 50/2 SLIC must be protected against overvoltages on the telephone line caused by lightning, ac power contact and induction. Refer to Maximum Ratings, TIPX and RINGX terminals, for maximum allowable continuous and transient currents that may be applied to the SLIC. Secondary Protection The circuit shown in figure 12 utilizes series resistors together with a programmable overvoltage protector (e.g. PowerInnovations TISPPBL2), serving as a secondary protection.
Control Inputs
The PBL 386 50/2 SLIC have three digital control inputs, C1, C2 and C3. A decoder in the SLIC interprets the control input condition and sets up the commanded operating state. C1 to C3 are internal pull-up inputs. Open Circuit State In the Open Circuit State the TIPX and RINGX line drive amplifiers as well as other circuit blocks are powered down. This causes the SLIC to present a high impedance to the line. Power dissipation is at a minimum and no detectors are active.
15
PBL 386 50/2
The TISPPBL2 is a dual forwardconducting buffered p-gate overvoltage protector. The protector gate references the protection (clamping) voltage to negative supply voltage (i e the battery voltage, VB ). As the protection voltage will track the negative supply voltage the overvoltage stress on the SLIC is minimized. Positive overvoltages are clamped to ground by a diode. Negative overvoltages are initially clamped close to the SLIC negative supply rail voltage and the protector will crowbar into a low voltage on-state condition, by firing an internal thyristor. A gate decoupling capacitor, CGG, is needed to carry enough charge to supply a high enough current to quickly turn on the thyristor in the protector. CGG shall be placed close to the overvoltage protection device. Without the capacitor even the low inductance in the track to the VBat supply will limit the current and delay the activation of the thyristor clamp. The fuse resistors RF serve the dual purposes of being non- destructive energy dissipators, when transients are clamped and of being fuses, when the line is exposed to a power cross. If a PTC is choosen for RF, note that it is important to always use PTCs in series with resistors not sensitive to temperature, as the PTC will act as a capacitance for fast transients and therefore will not protect the SLIC.
Power-up Sequence
No special power-up sequence is necessary except that ground has to be present before all power supply voltages.
Printed Circuit Board Layout
Care in PCB layout is essential for proper function. The components connecting to the RSN input should be placed in close proximity to that pin, so that no interference is injected into the RSN pin. Ground plane surrounding the RSN pin is advisable. Analog ground (AGND) should be connected to battery ground (BGND) on the PCB in one point. The capacitors for the battery should be connected with short wide leads of the same length.
Ordering Information
Package Temp. Range Part No.
24 pin SSOP Tape & Reel 0 - +70 C 24 pin SOIC Tube 24 pin SOIC Tape & Reel 28 pin PLCC Tube 0 - +70 C 0 - +70 C 0 - +70 C
PBL 386 50/2SHT PBL 386 50/2SOS PBL 386 50/2SOT PBL 386 50/2QNS PBL 386 50/2QNT
28 pin PLCC Tape & Reel 0 - +70 C
Information given in this data sheet is believed to be accurate and reliable. However no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Ericsson Microelectronics. These products are sold only according to Ericsson Microelectronics' general conditions of sale, unless otherwise confirmed in writing.
Specifications subject to change without notice. 1522-PBL 386 50/2 Uen Rev. A (c) Ericsson Microelectronics AB 1999 This product is an original Ericsson product protected by US, European and other patents.
Ericsson Microelectronics AB SE-164 81 Kista-Stockholm, Sweden Telephone: +46 8 757 50 00 16

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